1. Field of the Invention
The invention relates to a method for forming an isolation region on a silicon substrate in a semiconductor device, and more particularly, to a forming method for an isolation region between device components which region consists of a LOCOS layer and provides isolation between device-formed regions in a semiconductor device.
2. Description of the Related Art
An isolation region between device component in a semiconductor device is conventionally formed in such a manner that a silicon oxide layer 12 and a silicon nitride layer 13 are laminated in the order on a silicon substrate 11 as shown in FIG. 4(a), that layers are etched in a predetermined pattern to expose a silicon surface as shown in FIG. 4(b), impurities are fed through the exposed silicon surface to form a P.sup.- layer 14 of a channel stopper as shown in FIG. 4(c), and the local oxidation of silicon isolation using SiN layer 13 as a mask (LOCOS method) is carried out to form a silicon oxide layer 15 as shown in FIG. 4(d).
In recent years, as devices are further subminiaturized, it is required to form an isolation region between device components in submicron width. However, the submicron isolation region has a problem that the resistibility to punch-through between device components is deteriorated due to a short channel effect.
Meanwhile, a high voltage device is required to have higher values of a field reverse voltage and a breakdown voltage of n.sup.+ /p junction. It is necessary to reduce the amount of impurities in the channel stopper region for raising the breakdown voltage of n.sup.+ /p junction. In this case, there occurs another problem such as the field reverse voltage lowers. Conventionally, an oxide layer according to the LOCOS method is made thicker to mitigate the problem, resulting in a larger width of birdsbeak (an unnecessary oxidized region in a bird's beak-like shape) and that it is not conformable to further subminiaturize devices.
In this regard, the birdsbeak widths may be made smaller by changing specific conditions for the LOCOS method. However, the isolation region with the birdsbeak of smaller width has an acute rise as shown in FIG. 5 (a) and therefore, the silicon oxide isolation region 15 is stressed by the edge portion of the silicon nitride layer 13 (arrow 16) under growing and also a steep step 17 having a residual stress is developed after the removal of the silicon nitride layer 13.
Related to this, such a proposal has been made that an isotropic etching is applied to the surface of a semiconductor substrate before subjected to the LOCOS method to form a recess extending to and under an edge of a patterned silicon nitride layer formed as a mask on the substrate, and thereafter a LOCOS oxide layer is grown and formed at the recess, so that there is formed an isolation region free of a steep rise and mitigated in stress from the pattern end. (Japanese Unexamined Patent Publication No. 280437/1988).
An object of the invention is to provide an improved LOCOS method for forming an isolation region which has a smaller width and is further mitigated in stress by the end of the patterned silicon nitride layer used as a mask.